(a). Field of the Invention
This invention relates to a digital display device, and more particularly, to a method for generating a video clock for the digital display device.
(b). Description of the Prior Arts
A digital display device, such as liquid crystal display (LCD) monitor and plasma display panel (PDP) monitor, utilizes a display controller for converting received image data into a series of image frames for displaying on its panel. Each image frame includes a plurality of pixels. The display controller generates an output clock for outputting the pixels to the panel. FIG. 1 illustrates a diagram of the frame format. As shown in FIG. 1, a frame includes an image area 11 and a porch area 12. The image area 11 comprises a plurality of active pixels, and the porch area 12 comprises a plurality of inactive pixels, which contain no image data. The display controller outputs an image frame to the panel in accordance with an output vertical synchronization (Vsync) signal and an output enable signal. The frequency of the output vertical synchronization signal is equal to the frame rate. When the output enable signal is “Enable”, the active pixels of the image frame are outputted and displayed on the panel. On the contrary, when the output enable signal is “Disable”, the inactive pixels of the image frame are outputted. The amount of total pixels (active pixel and inactive pixel) of the image frame multiplied by the period of the output clock is equal to the period of the output vertical synchronization signal.
U.S. Pat. No. 5,739,867 discloses a relationship of an input video clock and an output video clock. However, generally speaking, the input video clock or the output video clock or both may have a jitter or drift and cannot have a fixed period, so an associated image frame cannot be displayed in a fixed format actually. That is, the amount of total pixels of the associated image frame is not fixed in the prior art (i.e., the amount of pixels of the last horizontal line of the image frame is not fixed). In addition, different kinds of panels may have different timing constraints. The timing constraint for a panel means the panel can only receive and identify an image frame with a special frame format (for example, the total amount of pixels of the image frame must be a multiple of four). When the format of a received frame does not match the special frame format, the panel cannot process it accurately. The conventional display controller cannot completely conform to the timing constraints of different kinds of panels.